Error (10219): Verilog HDL Continuous Assignment error at Mux.v(19): object "muxout" on left-hand side of assignment must have a net type

Question

I want to make Frequency Divider with Counter and MUX.

I make 3 module for project

// 4-bit Counter

module Counter (input clk, input reset, output reg[3:0] out);

   always@(posedge clk or posedge reset)
   begin
      if(reset)
         out = 4'b0000; 
      else
      begin
         if(clk)
            if(out < 4'b1111)
            out = out + 4'b0001;
            else
            out = 4'b0000;
      end
   end


endmodule

//module 4by1 Mux

module Mux (input [3:0] muxin , input [1:0] sel, output reg muxout);


   function _4by1mux;

      input [3:0] muxin;
      input [1:0] sel;

      case (sel)
         2'b00 : _4by1mux = muxin[0];
         2'b01 : _4by1mux = muxin[1];
         2'b10 : _4by1mux = muxin[2];
         2'b11 : _4by1mux = muxin[3];
      endcase
   endfunction

   assign muxout = _4by1mux(muxin, sel);


endmodule

//module freqDivider

 module freqDivider(input clk, input reset, input [1:0] sel, output reg muxout);

   wire [3:0]counterbus;

   Counter ct1 (clk, reset, counterbus);
   Mux mux1 (counterbus, sel, muxout);

endmodule

module freqDivider is top, and I call module Counter and Mux

but module Mux has problem with

Error (10219): Verilog HDL Continuous Assignment error at Mux.v(19):
object "muxout" on left-hand side of assignment must have a net type

this error

ps. input sel will be changed by time

please format you code using Cntrl + K. Also please explain your problem in detail and also where you need the help for resolution of your issue — mhasan
sorry this is my first time coding and I think output 'muxout' can't be assigned.... but why? — KKR
FYI: not related to your problem statement, but you should remove the line if(clk). Simulations will run fine but most synthesizers will consider all signals uses in a procedural blocks (aka always @(posedge/negedge ...)) sensitivity list and used in the body as asynchronous inputs. Without the line if(clk) you Counter module will simulate the same and will synthesize correctly — Greg

Unn Unn · Accepted Answer · 2016-10-02T10:14:39

The error is a result of the muxout output having type reg instead of type wire. In verilog, lines can have two overarching types, either nets (like wire type) or variables (like reg types). To assign values/logic to net types, you need to use assign statements and not always blocks. To assign values/logic to variable types, you can only use always blocks and not assign statements. So, you can either make your assign in the Mux module an always block or, for an easier solution, don't make the muxout output a reg, just leave out the reg keyword and it will be a wire.

Error (10219): Verilog HDL Continuous Assignment error at Mux.v(19): object "muxout" on left-hand side of assignment must have a net type

2 Answers