I came across a constraint which was behaving weirdly (illustrated below) :
class A;
rand bit[3:0] a,b,c,d;
constraint c_abcd{
2<a<b<c<d<20;
}
endclass : A
I know that this is not the right way to specify that constraint and that we need to split it up into multiple constraints. But I expected it to give an error. Instead, it runs without any error and I could see different values for a,b,c,d being generated.
These numbers initially seem to be random, but I guess the system verilog solver behaves in a predictable manner to tackle these constraints.
So can you explain how this is solved? When I randomize with the above constraint, I get the following output :
a = 1101;
b = 0101;
c = 0111;
d = 1100;
Thank You