Verilog 4 bit comparator = not working properly

Question

As my first program in verilog, I wrote a 4 bit comparator, made of individual 1 bit ones. I can't figure out why when Eo = 1, Lo = 1. I've been writing this in modelsim, and am new to the debug tools.

The code I wrote was based on the logic diagram on http://www.onsemi.com/pub_link/Collateral/MC14585B-D.PDF

// 1 Bit comparator
module comparator_1(A, B, L, E, G);
    input A, B; // 2 bits to be compared
    output L, E, G; // 3 possible outputs
    wire s1, s2;    // connecting wires for inverters

    not X1 (s1, A); // create inverter
    not X2 (s2, B);
    nand X3 (L, s1, B);
    nand X4 (G, s2, A);
    nand X5 (E, L, G);


endmodule


//4 bit comparator
module comparator_4(Lo, Eo, Go, A, B, Li, Ei, Gi);
    input [3:0] A; input [3:0] B;   //4 bit inputs 
    input Li, Gi, Ei;       //A<B, A=B, A>B inputs
    output Lo, Go, Eo;      //A<B, A=B, A>B outputs from chip
    wire [3:0]L; wire [3:0]E; wire [3:0]G;  //A<B, A=B, A>B outputs from individual comparators
    wire s0, s1, s2, s3, s4, s5, s6, s7, s8;

    // Set up individual 1 bit converters   
    comparator_1 comp0(A[0], B[0], L[0], E[0], G[0]);
    comparator_1 comp1(A[1], B[1], L[1], E[1], G[1]);
    comparator_1 comp2(A[2], B[2], L[2], E[2], G[2]);
    comparator_1 comp3(A[3], B[3], L[3], E[3], G[3]);

    // Gate logic from schematic

    or X1(s3, E[3], L[2]);
    or X2(s2, E[3], E[2], L[1]);
    or X3(s1, E[3], E[2], E[1], L[0]);
    or X4(s0, E[3], E[2], E[1], E[0], Li);
    nor X5(s4, E[3], E[2], E[1], E[0], Ei);
    nand X6(s5, L[3], s0, s1, s2, s3);
    nor X7(Go, s5, s4);


    assign Eo = s4;
    assign Lo = s5;

endmodule

Thanks

The schematic shows all the ors feeding into a nand, and all the nands feeding into a nor, which is what I have. Sorry for the terrible naming conventions. — Sean W
There's a few nots in the schematic that don't seem to be in the code. e.g. Li and Ei go through a not at the start. And all the outputs go through a not at the end. Did you optimize that out somehow? — samgak
Is that not a double inverter at the end? If not, that could be the whole problem, as I originally had the inverters on the inputs of those 2. — Sean W

Rich Maes Rich Maes · Accepted Answer · 2016-07-27T22:55:56

Based on the truth table, I would have described your Eo condition as

AND(s4,E[3], E[2], E[1], E[0], Ei);
assign E0 = s4;

In my mind, I am sure why that truth table assigns the possible output of A < B == 1 and A=B == 1 for the cascading inputs. That says it is both less than and equal. Bogus logic IMHO, but perhaps there are uses that I am not aware of. But the above statement for Eo will cover you in both cases, where all equals are asserted and the cascaded input is asserted as well.

Can I ask if you tried to write this at a higher level? I got confused with all the NOR and OR's.

module comparator_4(Lo, Eo, Go, A, B, Li, Ei, Gi);
    input [3:0] A; input [3:0] B;   //4 bit inputs 
    input Li, Gi, Ei;       //A<B, A=B, A>B inputs
    output Lo, Go, Eo;      //A<B, A=B, A>B outputs from chip 
    begin
    Eo = A==B & Ei;
    Lo = A<B & Li;
    Go = (A>B & Gi) || (A==B & ~Li & ~Ei);  // Last term covers weird case
    end
end module

I don't have time to check it out, but I think this would do the job.

Verilog 4 bit comparator = not working properly

2 Answers