I am designing a processor based on the Altera DE1 board. My biggest concern is power management. I understand that DE1 board has 3 clock inputs and an external clock input that may be used in my design. However, I would be using only one of these at a time.
Is there any way to turn unused clocks off and only turn them on once they are needed? From the user manual, clock enable for the 3 clock inputs are shorted to Vcc.
The power consumption of the 3 external clock generators are unlikely to be the biggest power drains in a system using the DE1 boards, since you are very likely to have many other unused parts on the DE1 board that will consume even more power than the extra clock generators.
If the a clock is unused inside the FPGA, then the power consumption in the FPGA by having a clock signal input is going to be minimal, since the clock is not distributed internally in the FPGA, thus not burning much power.
