Verilog Decoder with single inputs/outputs, not vector

Question

I found this verilog code for a thermometric decoder (in code encoder, but this is wrong).

I want to adapt it for cadence, to generate a netlist from it. My problem is, that the actual code generates a [7:0] + 1 input and a [3:0] output in cadence.

What I want, is a module with 8 + 1 single inputs and 4 single outputs:

module thermometer_encoder_8bit(
 out0,out1,out2,out3, //  4-bit binary Output
 in0,in1,in2,in3,in4,in5,in6,in7, //  8-bit Input
 enable       //  Enable for the encoder
 );

 input  enable;
 input in0,in1,in2,in3,in4,in5,in6,in7;
 output out0,out1,out2,out3;

 reg out0,out1,out2,out3;
 ... 

this is the actual, unadapted code:

module thermometer_encoder_8bit(
  binary_out , //  4 bit binary Output
  encoder_in , //  8-bit Input
  enable       //  Enable for the encoder
  );
  output [3:0] binary_out  ;
  input  enable ; 
  input [7:0] encoder_in ; 

  reg [3:0] binary_out ;

  always @ (enable or encoder_in)
  begin
  binary_out = 0;                 // 0000 0000
  if (enable) begin
     case (encoder_in) 

       8'b00000001 : binary_out = 1;  // 0000 0001
       8'b00000011 : binary_out = 2;  // 0000 0011
       8'b00000111 : binary_out = 3;  // 0000 0111
       8'b00001111 : binary_out = 4;  // 0000 1111
       8'b00011111 : binary_out = 5;  // 0001 1111
       8'b00111111 : binary_out = 6;  // 0011 1111
       8'b01111111 : binary_out = 7;  // 0111 1111
       8'b11111111 : binary_out = 8;  // 0000 1111

     endcase
   end
  end

endmodule

Is there any possibility, to do this in an easy way?

Greetings, DaHomer

Answer 1

First thing is, I dont see a default statement.

If you are sure encoder_in contains only those numbers mentioned in the case statement, you can use something like this. binary_out = $clog2(encoder_in + 1)

Answer 2

I would have modified the existing code with your required inputs and outputs and then made a assignments to interface the existing logic to the new ins and outs. I haven't compiled this, so take with a grain of salt.

module thermometer_encoder_8to4(
  out0 , //  4 bit binary Output
  out1 ,
  out2 ,
  out3 ,
  in0 , //  8-bit Input
  in1,
  in2,
  in3
  in4,
  in5,
  in6,
  in7
  enable       //  Enable for the encoder
  );
  output out0  ;
  output out1;
  output out2;
  output out3;
  input  enable ; 
  input in0;
  input in1;
  input in2;
  input in3;
  input in4;
  input in5;
  input in6;
  input in7;

  // Keep the binary_out and use this to drive the new non-vector outs... 
  reg [3:0] binary_out ;

  // Here is where we assign the non-vector outs and non-vector ins.
  wire [7:0] encoder_in = {in7,in6,in5,in4,in3,in2,in1,in0};
  assign {out3,out2,out1,out0} = binary_out;

  always @ (enable or encoder_in)
  begin
  binary_out = 0;                 // 0000 0000
  if (enable) begin
     case (encoder_in) 

       8'b00000001 : binary_out = 1;  // 0000 0001
       8'b00000011 : binary_out = 2;  // 0000 0011
       8'b00000111 : binary_out = 3;  // 0000 0111
       8'b00001111 : binary_out = 4;  // 0000 1111
       8'b00011111 : binary_out = 5;  // 0001 1111
       8'b00111111 : binary_out = 6;  // 0011 1111
       8'b01111111 : binary_out = 7;  // 0111 1111
       8'b11111111 : binary_out = 8;  // 0000 1111

     endcase
   end
  end

endmodule

I'll add the following, noting that this wasn't specifically your question, but wonder if this might be of use to you.

At the instantiation, of the original module, you could have just assigned the individual ins and outs as a concatenated vectors.

thermometer_encoder_8bit u0_ thermometer_encoder_8bit 
(
   binary_out ({out0,out1,out2,out3}), //  4-bit binary Output
   encoder_in ({in0,in1,in2,in3,in4,in5,in6,in7}), //  8-bit Input
   enable     (enable)  //  Enable for the encoder
);