Makefile Dependicies

0
votes

I need help creating a Makefile.

My files:

g.c

v.h

v.c

main() is inside g.c, which includes v.h

My Makefile looks like this:

all: bin/v bin/g

bin/v: v.c
    cc v.c -o bin/v -Wall

bin/g: g.c
    cc g.c -o bin/g -D_REENTRANT -lpthread -Wall

PHONY: all

When running make all, I get tons of errors:

relocation X has invalid symbol index Y

followed by

/usr/lib/gcc/x86_64-linux-gnu/4.8/../../../x86_64-linux-gnu/crt1.o: In function `_start':

(.text+0x20): undefined reference to `main' collect2: error: ld returned 1 exit status

What should my Makefile look like?

Thanks in advance!

2
clinuxmakefile

2 Answers

1
votes

because you are trying to generate an executable when you are doing 

bin/v: v.c
    cc v.c -o bin/v -Wall

You need to give flag -c to just compile , since v.c doesn't contain any main that's why Linker is giving error. In layman terms, Linker & loaders comes into the picture of compilation when then need to generate executable

3
votes

I don't know why are you getting this linker/loader error, may be you are not mentioning v.h with v.c but this is a sample your Makefile should look like which I used to use once.

Consider you have a directory name folder and you have placed all your files main.c , v.h and v.c in that directory. Then create a file by name Makefile in that directory. Contents of the Makefile should be as follow 

all: main.out 

main.out: main.c v.o
      gcc -o main.out main.c v.o

v.o:   v.c v.h
     gcc -c v.c 

clean: 
     rm -rf main.out *.o