On ARM Cortex-R4F, when I disable instruction and data cache using SCTLR register bits I and C, what happens to MPU region that defines region attribute as cachable (write-back)? Would it be ignored since global cache is disabled or would it result in unknown behavior?
3
votes
Doesn't the Cortex-R4F have an MMU, not just an MPU?
– too honest for this site
@Olaf nope, none of the R-class parts have an MMU (most of the applications they're targeted at wouldn't appreciate the latency and generally-unpredictable nature of TLB misses).
– Notlikethat
@Notlikethat: You are right about the MPU, just checked that. But an MMU can be very well deterministic if you use a statically programmed TLB. But agreed that would be much the same as the simpler MPU with more silicon space.
– too honest for this site
1 Answers
3
votes
Under the ARMv7-A/R architecture, it's actually implementation-defined whether or not the SCTLR C and I bits affect the attributes generated by an enabled MMU/MPU. However, judging by the description of the default memory map attributes in the Cortex-R4 TRM, it looks to be in the "behaves as expected" camp, where SCTLR.C = 0 means accesses to any Normal memory region come out as Non-cacheable.
Even if that weren't the case, the alternative would just be that the bit has no effect, and the MMU/MPU attributes are used. Fortunately there's no scope for completely unpredictable behaviour here.
That said, the hairier aspect to consider is that whilst Non-cacheable accesses are guaranteed not to allocate in the cache, it is implementation defined whether they can still hit if a valid entry for that location happens to be present. Thus if you're turning the cache off after making any Cacheable accesses you'll want to immediately clean and invalidate the whole thing before going any further - I'm not sure which side of that implementation choice Cortex-R4 falls, but either way I wouldn't take the risk of not doing so.
