passing multidimensional array passing in systemverilog

Question

I knew that in verilog, multidimensional array cannot be passed through the module port. I heard this is allowed in systemverilog, and it is the very reason I started to use systemverilog. However, for the following code, I still encounter the error shown below for both x and y.

A reference to an entire array is not permitted in this context [Systemverilog]

Here is the code.

module Chien(p, clk, reset, load);
        wire [`m - 1 : 0] x [0 : `t - 1];
        wire [`m - 1 : 0] y [0 : `t - 1][0 : `col];
        mul_array mularray0(x, y);
endmodule

I am using ncverilog for simulation, and I take the -sv option. Is there any problem with my code, or it is the simulator's problem?

Thanks

dave_59 dave_59 · Accepted Answer · 2016-03-06T22:30:56

Works fine for me in Modelsim/Questa, except you are required to declare the ports in your port list and not just have a positional list of ports.

module Chien(input wire p, clk, reset, load);

Also since I have your attention, try not to use macros in your type declarations. Better to have parameters and typedefs

package pkg;
  parameter int col = 4, m = 5, t = 6;
  typedef logic [m-1:0] array_t[t];
endpackage 

module Chien(input p, clk, reset, load);
        import pkg::*;
        wire array_t x;
        wire array_t y [col];
        mul_array mularray0(x, y);
endmodule

passing multidimensional array passing in systemverilog

1 Answers