GNU make wildcard variable target

Question

I'm trying to create a makefile with wildcard targets but the wildcards should match on variables.

So I have a makefile like this:

A_OUT := bin/a
B_OUT := bin/b

# This does not work
$(%_OUT):
    @echo $@

Output:

$ make bin/a
make: *** No rule to make target 'bin/a'.  Stop.

I can not use bin/%: because the variables may point to another directory.

Is there any way to do this in GNU make?

Why can't you use bin/%? What does the target being a directory change about this? What do you plan on doing in the target that your proposed snippet would do that using bin/% doesn't? — Etan Reisner
@EtanReisner I wouldn't be able to call it like this: make A_OUT=anotherdir/a anotherdir/a — das_j

Etan Reisner Etan Reisner · Accepted Answer · 2016-03-06T20:28:12

If you just want a list of targets to all have the same recipe then just list them all in the same rule definition. e.g.

$(A_OUT) $(B_OUT):
        @echo $@

You can use a variable for that too:

A_OUT := bin/a
TGTS += $(A_OUT)
B_OUT := bin/b
TGTS += $(B_OUT)

$(TGTS):
        @echo $@

Depending on what you need you may also want to use Static Pattern Rules

$(TGTS) : bin/% : 
        @echo $@ : $*