Verilog replication with macro

0
votes

I have a sys_defs.vh header file with the macro:

`define REG_WIDTH 5

and I'm trying to compare a bus of the same width like so:

input [2:0][`REG_WIDTH-1:0]           aregs_in,
...
if(aregs_in[i] != {`REG_WIDTH{1}})
  //do stuff

but I get the following warning when I try to simulate

Warning-[CWUC] Concatenations with unsized constants. An unsized constant '1' is used in the concatenation. The unsized constant will be used as a 32-bit constant.

Basically I'm just trying to compare it to 111111 where the # of one's is macro-defined

2
verilogsystem-verilog

2 Answers

3
votes

In Verilog 1 by itself infers a 32-bit decimal with the value one. You want 1'b1 for a single bit.

input [2:0][`REG_WIDTH-1:0]           aregs_in,
...
if(aregs_in[i] != {`REG_WIDTH{1'b1}})
  //do stuff
3
votes

In Verilog you could do

   if(~&aregs_in[i]) //~& is the NAND operator
      // do stuff

In SystemVerilog, this would be more descriptive

  if(aregs_in[i] != '1) // '1 means 'fill with 1's'
      // do stuff