VHDL sequential conditional signal assignment statement error

Question

In my VHDL code I have an error in sig_out_real <= X"00" & sig_in when sig_in(7)='0' else X"ff" & sig_in;.

I don't think it is a syntax error. But Quartus shows an error at that point.

I don`t understand why it's an error.

Can anyone provide information:

-- Error--

Error (10500): VHDL syntax error at S8BT16B.vhd(35) near text "when"; expecting ";"

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
use work.fft_package.all;

entity S8BT16B is
port( 
    clk_50 : in std_logic;
    clk_baud : in std_logic;
    main_reset : in std_logic;
    enable : in std_logic;
    sig_in : in signed (7 downto 0);
    sig_out : out complex;
    valid_output : out std_logic
  );
end S8BT16B; 

architecture Behavioral of S8BT16B is
type state is (idle,start);
signal state_reg, next_state_reg : state;
signal sig_out_real : signed(15 downto 0);  
begin           
state_change : process(clk_50, main_reset)
begin
    if (main_reset = '1' or enable = '0') then
        state_reg <= idle;
    elsif (main_reset ='0' and enable = '1') then
        state_reg <= next_state_reg;
    end if;
end process;

S8BT16B_active : process(clk_baud, state_reg)
begin       
    if (state_reg = idle) then
        sig_out_real <="0000000000000000";
        sig_out <=(sig_out_real,"0000000000000000");
        next_state_reg <= start;
        valid_output <= '0';
    elsif (state_reg = start and enable = '1') then         
        sig_out_real <= X"00" & sig_in when sig_in(7)='0' else X"ff" & sig_in;
        sig_out <= (signed_converted_input, "0000000000000000");
        next_state_reg <= idle;
        valid_output <= '1';
    end if;     
end process;
end Behavioral;

Please take care when using VHDL'08 features like when...else in process statements. This is supported in Quartus when you enable VHDL'08 for synthesis in your project. But other VHDL'08 features might not be supported, giving wired error messages. Also always try to create a minimal, complete and verifiable example when asking here. — Martin Zabel

Unknown Unknown · Accepted Answer · 2016-02-14T07:06:59

You code does not present a Minimal, Complete, and Verifiable example.

The package fft_package presumably containing the type declaration for complex is not present.

The declaration for signed_converted_input is also not present.

A sequential conditional signal assignment statement is only available in VHDL-2008.

There's a good argument to be made that the Synopsys packages std_logic_arith and std_logic_signed are not compatible with IEEE Std 1076-2008's defined package std_logic_1164. It's possible they've been re-written to accomidate the new definitions of std_logic_vector and std_ulogic vector, although not if they work without -2008 compatibility, without some serious automagic on the part of ALDEC.

If passing a -2008 compatibility flag doesn't fix things for you the simplest thing you can do is replace the sequential conditional signal assignment statement with two simple signal assignment statements inside an if statement:

library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
use ieee.std_logic_arith.all;

package fft_package is
    type complex is record
        sig_real:       signed (15 downto 0);
        sig_imaginary:  signed (15 downto 0);
    end record;
    constant signed_converted_input:    signed (15 downto 0) := (others => '0');
end package;

library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use work.fft_package.all;

entity S8BT16B is
port( 
    clk_50:      in  std_logic;
    clk_baud:    in  std_logic;
    main_reset:  in  std_logic;
    enable:      in  std_logic;
    sig_in:      in  signed (7 downto 0);
    sig_out:     out complex;
    valid_output:  out std_logic
  );
end S8BT16B; 

architecture Behavioral of S8BT16B is
    type state is (idle,start);
    signal state_reg, next_state_reg:   state;
    signal sig_out_real:                signed(15 downto 0);  
begin  

state_change:  
process(clk_50, main_reset)
    begin
        if (main_reset = '1' or enable = '0') then
            state_reg <= idle;
        elsif (main_reset ='0' and enable = '1') then
            state_reg <= next_state_reg;
        end if;
    end process;

S8BT16B_active:  
    process(clk_baud, state_reg)
    begin       
        if state_reg = idle then
            sig_out_real <= "0000000000000000";
            sig_out <=(sig_out_real,"0000000000000000");
            next_state_reg <= start;
            valid_output <= '0';
        elsif state_reg = start and enable = '1' then         
            -- sig_out_real <= X"00" & sig_in when sig_in(7)='0' else
            --                 X"ff" & sig_in;
            if sig_in(7) = '0' then
                sig_out_real <= X"00" & sig_in;
            else 
                sig_out_real <= X"ff" & sig_in;
            end if;

            sig_out <= (signed_converted_input, "0000000000000000");
            next_state_reg <= idle;
            valid_output <= '1';
        end if;     
    end process;
end Behavioral;

This code analyzes, elaborates and simulates (to show there are no length mismatches without regards to sig_in(7) = '0') while any claim to it's functionality is not made. The length looks right in the assignments to sig_out_real.

And of course without seeing the actual contents of your package fft_package claims to syntax and semantic validity can't be absolutely made (the faux package and your modified code are consistent with each other).

VHDL sequential conditional signal assignment statement error

1 Answers