VHDL Vector Array

Question

I am attempting to create an array of vectors in VHDL however I am getting an error in modelsim. I have:

type   read_data_array is array (0 to 73) of std_logic_vector(7 downto 0);    
signal reg_data_stream              : read_data_array;

I store data into the array by:

reg_data_stream(counter) <= read_data;

"read_data" is that of std_logic_vector(7 downto 0) and "counter" is a basic counter that increments from 0.

subtype byte is std_logic_vector(7 downto 0); type read_data_array is array (0 to 73) of byte; Or tell us what the actual error message says... — user_1818839
And the declaration for read_data and count as well as the actual error message. — user1155120
Out of the top of my head, I'd say that counter is not an integer and you're missing a to_integer(...) statement, but I could be wrong. — fpga_magik

chrisvp chrisvp · Accepted Answer · 2016-08-20T14:59:58

To index an array or a vector, VHDL expects an integer. If counter is a std_logic_vector, try:

to_integer(unsigned(counter)) <= read_data;