I have a Simulink model with master clock value of 4410 Hz. I know for a fact that computation time of some algorithms (e.g. cubic spline interpolation on a 4410 sample frame being accumulated in real-time) is much longer than the master time period (i.e. computation time of spline is cca 0.7 seconds). I would expect Simulink to output frame elements AFTER initial 1 second + propagation time delay (like in hardware languages, e.g. VHDL), but it actually starts outputting the elements of the frame just after one seconds (which is the length of frame, 4410/4410 seconds). This wouldn't be a problem if my output values weren't unexpected/wrong.
How does Simulink build the simulation in this case? It would appear that it stops the simulation for larger computation times, then continues it afterwards.