what is the difference between " CSD multiplication" "verilog multiplication"?

Question

I have seen 2 posting at here Verilog - Floating points multiplication

and how can I apply fixed fraction to the integer

As you can se, those are all regarding of verilog fraction multiplication. But I can confused that Mogan's answer of this.

reg [7:0] a = 0010_1000; reg [7:0] b = 0010_1000;

How can he got this binary? Is this CSD terms?

Update

I know well interger * CSD term. It will converted like this figure( integer >>2)+(integer>> 5).. But I want to kow CSD term * CSD term.

What about this?

wire [11:0] y;
wire [11:0] x;
wire [11:0] z;
y= {3.1, 10'b0}
x= {2.5, 10'b0}
z= y*x
z = z >> 10;

Now I think this is little a bit cost than your way. you can use just just one multiplication. But my method is need shifter to right.

Looking at this answer where the question talks about multiplying 2.5 * 2.5. The answer describes how to interpret an 8 bit number comprised of 4 integer bits and 4 fractional bits. using _ as a binary point marker 0010_1000 represents 2.5. CSD would contain negative terms denoted by 1 BAR (T) this is just a binary word with 4 fractional places. If you could elaborate on which part your stuck I can try explain it better. — Morgan
@Morgan My stuck point is that what if I want to multiplication calculate fraction number like 2.5 x 2.5 then how can I use CSD term in verilog? For example 2.5 is 0010_0111 and this is able to convert CSD 0010_100T. As you already know the T is just expression, it does not use in verilog. So my question is how to we apply CSD term numbers into verilog multiplication? CSD term x CSD term. — bural
What do you mean by CSD term, the full CSD number (0010_100T) or just a single part of it (T, -2^4)? — Morgan
@Morgan I meant full numver T. <=Here is used T. What if you have to multiplication by using two CSD number, then how do you calculate? Actually it does not matter single or full. Does'n it? For example 0010_100T * 0010_100T — bural
How are you representing 0010_100T in verilog. I am not aware of why you would end up with two CSD formats for multiplication. as the CSD conversion of a number is designed to make multiplication easy. — Morgan

Morgan Morgan · Accepted Answer · 2015-12-21T11:23:11

To answer a question in a comment How to multiply 3.1*2.4 in Signed 4 int 4 frac wordlength.

3.1 => 0011_0001 (actually 3.0625) .1 is very difficult to represent in fixed point.
2.5 => 0010_1000

EDA Playground:

reg signed [15:0] mul;
initial begin
  mul = 8'sb0011_0001 * 8'sb0010_1000;
  $display("mul = %16b", mul);
end
//mul = 0000011110101000

Break down of result:

     2^ 76543210 -1-2-3-4-5
  mul = 00000111_ 1 0 1 0 1 000
2^2 + 2^1 + 2^0 + 2^-1 + 2^-3 2^-5
  4 +   2 +   1 + 0.5 +0.125 + 0.03125
              =======
              7.65625

On a normal calculator:

3.0625 * 2.5 => 7.65625

The rounding from 3.1 to 3.0625 caused this error 3.1*2.5 => 7.75, quantisation error of 0.09375.

what is the difference between " CSD multiplication" "verilog multiplication"?

Update

1 Answers