VHDL, Select Signal, Concatenating

Question

Need to understand how to use Selected Signal Assignment and include a 4-bit internal signal, called WXYZ, by concatenating W with X with Y with Z for the following Boolean algebra expression F(W,X,Y,Z)=Y'Z'+W'X'+X'Y

ENTITY Part_2A IS 
PORT(
    W, X, Y, Z  : IN STD_LOGIC;
    G1          : OUT STD_LOGIC);       
END Part_2A;

ARCHITECTURE sig OF Part_2A IS

SIGNAL inputs : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL outputs: STD_LOGIC;
BEGIN 
--Concatenate input ports into 4-bit signal
inputs <= W & X & Y & Z;
WITH inputs SELECT         
    outputs     <=  "1" when "0000",
                    "1" when "0001",
                    "1" when "0010",
                    "1" when "0011",
                    "1" when "0100",
                    "1" when "1000",
                    "1" when "1010",
                    "1" when "1011",
                    "1" when "1100",
                    "0" when others;
G1 <= outputs;
END sig;

Is there a question here or just a statement? See How to create a Minimal, Complete, and Verifiable example "Describe the problem. "It doesn't work" is not a problem statement. Tell us what the expected behavior should be. Tell us what the exact wording of the error message is, and which line of code is producing it. Put a brief summary of the problem in the title of your question." under Verifiable. — user1155120

Unknown Unknown · Accepted Answer · 2015-10-21T00:41:07

You can't ask any better than

Need to understand how to use Selected Signal Assignment and include a 4-bit internal signal, called WXYZ, by concatenating W with X with Y with Z for the following Boolean algebra expression F(W,X,Y,Z)=Y'Z'+W'X'+X'Y

I don't even see a question mark there.

With the addition of a context clause referencing IEEE library std_logic_1164 and converting the string literals "1" and "0" to character literals '1' and '0' (character literals are acceptable enumeration literals, std_ulogic the base type of std_logic is an enumerated scalar type) and we have something like:

library ieee;
use ieee.std_logic_1164.all;

entity part_2a is 
    port (
        w, x, y, z  : in std_logic;
        g1          : out std_logic
    );       
end entity part_2a;

architecture sig of part_2a is

    signal inputs : std_logic_vector(3 downto 0);
    signal outputs: std_logic;
begin 
--concatenate input ports into 4-bit signal

    inputs <= w & x & y & z;

    with inputs select         
        outputs <=  '1' when "0000",
                    '1' when "0001",
                    '1' when "0010",
                    '1' when "0011",
                    '1' when "0100",
                    '1' when "1000",
                    '1' when "1010",
                    '1' when "1011",
                    '1' when "1100",
                    '0' when others;
    g1 <= outputs;
end architecture sig;

Which analyzes without error.

You may have been mislead by your VHDL tool. There are some VHDL implementations that specifically complain about the type mismatch. For instance ghdl:

ghdl -a part_2a.vhdl
part_2a.vhdl:21:21: can't match string literal "1" with type enumeration subtype "std_logic"
part_2a.vhdl:22:21: can't match string literal "1" with type enumeration subtype "std_logic"
part_2a.vhdl:23:21: can't match string literal "1" with type enumeration subtype "std_logic"
part_2a.vhdl:24:21: can't match string literal "1" with type enumeration subtype "std_logic"
part_2a.vhdl:25:21: can't match string literal "1" with type enumeration subtype "std_logic"
part_2a.vhdl:26:21: can't match string literal "1" with type enumeration subtype "std_logic"
part_2a.vhdl:27:21: can't match string literal "1" with type enumeration subtype "std_logic"
part_2a.vhdl:28:21: can't match string literal "1" with type enumeration subtype "std_logic"
part_2a.vhdl:29:21: can't match string literal "1" with type enumeration subtype "std_logic"
part_2a.vhdl:30:21: can't match string literal "0" with type enumeration subtype "std_logic"
ghdl: compilation error

While some quit at the first error:

nvc -a part_2a.vhdl  
** Error: no one dimensional arrays of character type in context
       File part_2a.vhdl, Line 21  
       outputs     <=  "1" when "0000",  
                       ^^^

If you have one that simply points at the beginning of the statement

WITH inputs SELECT

With no useful information you might think it's a concatenation problem (depending on what the actual error message said). Which explains why a Minimal, Complete, and Verifiable example can be valuable.

Error messages tend to be distinct to a particular vendor, and tell what you trying to do.

VHDL, Select Signal, Concatenating

1 Answers