Duty Cycle adjustment Fast PWM Mode

0
votes

As per the datasheet of Atmega328, Timer0 fast PWM mode can be selected by setting WGM02:00 to either 011 or 111. When we set Fast PWM mode using 111, TOV Flag set on TOP. Also TOP is equal to OCR0A. Now ON time of PWM is controlled using OCRA. When compare match occurs, OCA0 is cleared (COM0A1:COM0A0 = 10) and it is set at the bottom. Now my question is if TCNT clears after reaching TOP (that is nothing but OCR0A), how can we alter On time with WGM02:00=111? I am not quite clear from data sheet. Even waveforms are also little confusing. Or is it that TCNT always counts from 0x00 to 0xff irrespective of TOV flag in this case?

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2
avratmegapwm

2 Answers

1
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Since OCRA is in use, you have to use the other OC registers, e.g. OCRB. OCA will still follow the directions given to it by COM0A, but is significantly less useful for that.

0
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While using the output compare unit register (OCR0A) to define the top value of the counter (WGM02:WGM00=111), you can only toggle the logical level at the corresponding pin (OCA0) when a compare match between TCNT0 & OCRA0 occurs. Hence, you can't control the duty cycle (always 50%). This is just like the ctc mode, except that the double buffering feature of the output compare unit is enabled in fast PWM mode. Look at the datasheet, the last paragraph in the description of fast PWM mode:

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle its logical level on each compare match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of fOx0 = fclk_I/O/2 when OCR0A is set to zero. This feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.

However, you can use timer 1 to control the frequency and the duty cycle, by setting the input capture unit register (ICR1) to define the TOP value of the counter, and then the output compare unit register (OCR1A) will be free to make the corresponding pin (OC1A) take action (set or clr) when a compare match occurs.