Generating a RISCV Rocket Chip with different cache sizes

Question

I am having problems changing parameters of the Rocket-Chip. I am trying to raise the number of sets for the L1 data and instruction cache. I am following this description: http://riscv.org/download.html#tab_rocket
The following codelines are the values I am trying to change in the file: Configs.scala which is located in the Rocket Chip Generator repository (rocket-chip/src/main/scala)

  knobValues = {
    case "NTILES" => 1
    case "NBANKS" => 1
    case "L1D_MSHRS" => 2
    case "L1D_SETS" => 64
    case "L1D_WAYS" => 4
    case "L1I_SETS" => 64
    case "L1I_WAYS" => 4
  }
)

Before I do any changes I can run the following command with no error:

make run-asm-tests

If I change LD1_SETS => 64 to LD1_SETS => 128 I get a lot of errors using the command above.

Do I have to set the Cache-Size somewhere different??

user2548418 user2548418 · Accepted Answer · 2015-08-11T16:32:26

Rocket uses a virtually-indexed, physically-tagged L1 data cache. Because of this, the size of a way must be less than the page size. The errors you are seeing are caused by asserts to enforce this. To get around this, I recommend increasing the number of ways (not the number of sets), or increasing the size of L2 to compensate.

This may seem like an odd requirement, but many processors have it. The L1 cache size is typically determined by the page size and the maximum associativity they can do without hurting the critical path.

Generating a RISCV Rocket Chip with different cache sizes

1 Answers