Modifying UVM sequence item variable

0
votes

I am writing a new sequence item that is extending from an existing sequence item. In the new sequence, I would like to extend the size of a variable in the existing sequence item, like so:

Existing:

rand bit [9:0] var_mem;

New:

rand bit [15:0] var_mem;

Whenever I run the sequence using the new extended sequence item, the transaction shows the size of var_mem as 10, not the expected 16. Is it possible to modify the size of a variable in the new extended sequence item, either in the sequence item or the corresponding sequence?

2
system-veriloguvm

2 Answers

1
votes

It is usually a bad idea to override variables in an extended class unless all methods that access the base variable are overridden as well. The UVM does not support this very well, especially if you are using the field automation macros.

Your options are to declare the variable with the maximum size in the base class, and use another variable to represent the actual size. That size variable can be used to constrain the value during randomization, as well as pack/unpack methods you provide.

Another option is to use a parameterized class that defined the variable width.

-1
votes

Try using the parameter instead of bits width. Here’s the snippet of the code for your reference 

class existing_seq extends uvm_sequences(response_item);
  rand bit [9:0] var_mem ;
endclass
class new_seq #(int size = 16) extends existing_seq;
  rand bit [size-1:0] var_mem ;
  existing_seq seq1;  
endclass