I basically have two vectors (type: integer, signed, unsigned, std_logic_vector, doesn't really matter for the imlementation).
Vector 1 has a static size of 16 (equals 1word). Vector 2 has a dynamic size of X*16 (equals X words) X is the dynamic parameter.
Now I want to have a construct where I can sum X words from vector 2 depending on the parameter X.
sth. like this:
vector_1 <= for i in 0 to X generate
vector_2(X*16+15 downto X*16) +
end generate;
Anyone can imagine something like this being possible in VHDL?
Cheers, Steffen
EDIT: Maybe to make it more clear, what I want to have:
accumulated_data <= std_logic_vector( signed(data_vector(0*16+15 downto 0*16)) +
signed(data_vector(1*16+15 downto 1*16)) +
...
signed(data_vector(X*16+15 downto X*16))
);
X is static at synth.
Xbe able to change during run time? You can't have a synthesisable VHDL construct whose size is dynamic during run time. - scary_jeffXbe? Is it feasible to have Vector 2 use block memory resource? - scary_jeff