Specman beginner's questions

Question

I am new to Specman. I have a couple of questions:

1. I am trying to use the agent methodology. After writing the env,agent,bfm etc - what is the recommended way to create clock and reset? by writing a tb.v (calling the top verilog module) or is there a better way?

2. How do I link the specman env file to the tb (or maybe its just enough to link the ports of the different specman files with a signals_map to the verilog files?

3. Most important how do I run the environment with irun? I was thinking of creating a file listing all the verilog files, e.g. - veri.lst the specman top shall import all the specman files, e.g - spec_top.e

   irun -access +wrc veri.lst spec_top.e

should be ok? should I mention the top level module in the command? Should I put the test name in a special way in the command?

Thanks alot for all the help!!

Answer 1

Cadence recommends driving clocks from inside an HDL testbench (i.e. written in Verilog in your case). This is because every time the simulator yields control to Specman to execute it wastes processor time. You want to minimize the number of switches as much as possible.

Linking the env to the TB is done by connecting the Verilog signals of interest to the corresponding Specman ports (using hdl_path()).

W.r.t. running it, there are 2 things to keep in mind. e code can be executed in compiled or in interpreted mode. Also, compiled code is faster, but can't be debugged. You have to tell irun what you want compiled and what you want interpreted:

irun -f veri.lst \
  compiled_top.e \
  -snload interpreted_top.e

What you typically compile are files which you don't expect to change (verification components that you buy or reuse from other projects, for example). The rest of your files you'd load interpreted to be able to easily debug.

Answer 2

Adding to Tudor's great answer -

First - yes, connecting The e TB to the DUT is done using hdl_path(), and connecting the ports to external. You usually would have one unit designated for the interface, so configuring it would look something like this:

extend signal_map {
    // name of the instance of the verilog module you interface
    keep hdl_path() == "sub_system_a"; 
    keep bind (sig_clock, external);
    // name of the clock signal
    keep sig_clock.hdl_path == "clk";
};

Please take a look in the IES release, at the UVM Examples.

They are in specman/uvm/uvm_examples

For example, check out the specman/uvm/uvm_examples/xserial/e/xserial_collector_h.e:

Answer 3

And about the clock -

Connecting a clock in the e TB to the design is very simple. Something like this -

unit synch {
    sig_clock : in simple_port of bit is instance;
    keep  bind(sig_clock, external);
    event clock is rise(sig_clock$) @sim;
    // can define also on fall or change 
};

Now the clock event can be used as sampling event for TCMs and Temporals. This is a simple fast way for using the clock in the TB.

Another way to use the clock, is more "acceleration ready". In this methodology, you would implement a clock agent in verilog, and it will provide "clock services" to the TB. According to this methodology, the TB will not have any "wait cycles" in it. instead - it will call the Clock Agent task "wait_cycles()" - and wait for indication that required number of clock cycles passed. This is a rather new methodology, oriented to be Acceleration Ready.

It will be demonstrated in the UVM Examples in next IES release, 15.1.

/efrat