I'm creating a hardware module that is using fixed point for its computations. But the input is floating point, and I thus wish to convert the floating point input into fixed point (Q8.8).
I've been trying to use is David Bishops library (http://vhdl.org/fphdl/) for floating points and fixed point. It works well in simulation, but not when I synthesize it. E.g. in the following code the output y is routed to ground when synthesized.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.float_pkg.all;
entity sigmoid is
Port (
clk : in std_logic;
x : in float32;
y : out sfixed(15 downto -16)
);
end sigmoid;
architecture Behavioral of sigmoid is
signal size : sfixed(15 downto -16);
begin
set_c: process(clk)
begin
if rising_edge(clk) then
y <= to_sfixed(x, size);
end if;
end process;
end Behavioral;
From what I've been reading on various forums and in the documentation, this code should synthesize fine. Also, fixed to float conversion using to_float(fixed) works just fine. Have I missed something? Are there other simple ways of implementing float -> fixed conversion?
ieee_proposed
available, with the functionality you expect? Differences in support of libraries between simulation and synthesis tools are a frequent cause of problems. What tools are you using? Do they have VHDL-2008 support? – Josh