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Suppose we have the following situation: 2 CPU wtih write buffers and MESI is used as the cache coherence protocol. And we have one shared cache line between the CPUs:

CPU1 cache: |I|I|S|I|I|

CPU2 cache: |I|I|S|I|I|

Now CPU1 decides to modify the shared line. It puts the change record to its write buffer and sends invalidation message to CPU2. CPU2 receives it and sends an acknowledgment:

CPU1 cache: |I|I|S|I|I|, CPU1 write buffer: change for the 3rd cache line

CPU2 cache: |I|I|I|I|I|

Is it right that on receiving the acknowledgment CPU1 doesn't have to flush the write buffer and change the cache line state to M(modified)? If not than let's go further.

Suppose now CPU2 wants to read this cache line again. Should snooping CPU1 intercept this read request, and flush buffer->flush cache line->send the last value of the cache line to CPU2? Or it might ignore it and CPU2 would still have the old value by asking the RAM(which wasn't changed yet)?

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1 Answers

1
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In the standard MESI protocol, there is no acknowledgment of of invalidate transactions. In your example, the cache line transitions to the M state in CPU1 and the write is retired from the write buffer.

When CPU2 does a read, CPU1 writes out the modified line to memory. CPU2 can get the value either from CPU1 or from memory (only after CPU1's write completes). The write to memory is needed because there there is no O (Owned) state.

There are protocols like the Dragon protocol that do use a signal to indicate if a cache line is shared or not.