Exclude some fields from randomization during a generation run

Question

I wan't to exclude some fields from randomization based on a certain condition that is itself determined during the same randomization run. This means I can't use rand_mode(0) as this needs to be called before a call to randomize().

Here's a simple example of what I mean. Let's say I have a class with 2 integer fields and a boolean that decides whether to randomize the second field or to keep its value constant (i.e. the one before a call to randomize()):

class some_item;
  rand bit do_rand_other_field;
  rand int some_field;
  rand int some_other_field;

  // ...
endclass

The only thing I can come up with is to declare an extra local field that will store the value of some_other_field before a randomization run:

class some_item;
  // ...

  local int some_other_field_init;

  function void pre_randomize();
    some_other_field_init = some_other_field;
  endfunction

  // ...
endclass

When do_rand_other_field is not true, I just constrain the field to take its initial value:

class some_item;
  // ...

  constraint randomize_some_other_field {
    if (!do_rand_other_field)
      some_other_field == some_other_field_init;
  }

  // ...
endclass

This works, but if I have many such conditionally randomized fields it can become inefficient to store and copy them all. I could declare these "initial" fields as static and this would reduce the memory consumption, but the run-time penalty of copying would still be there.

The randomization engine has to store these values somewhere, since in case of a constraint contradiction it will return the un-randomized object. I'd like to find a way to tap into these value. Is there any feature of the language that I overlooked that could help me do this?

A running example can be found on EDAPlayground: edaplayground.com/x/8nS — Tudor Timi

dave_59 dave_59 · Accepted Answer · 2015-03-24T17:07:11

There is no feature in SystemVerilog to do what you are asking for without either copying the states you potentially want to maintain, or separating into independent randomizations(separate random class objects or 2-pass on the same object)

The constraint solvers in SystemVerilog work conceptually by constructing the entire solution space first, then randomly picking one of the solutions. You cannot dynamically change the randomness of one of the variables during the solution space building process.

I suppose SystemVerilog could be enhanced so that referring to the previous value of an random variable could be used in a constraint as a state variable, but that would be several years away for you in any case.

Exclude some fields from randomization during a generation run

2 Answers