wait must contain condition clause with until keyword

Question

The following VHDL is to be used to test bench a booth multiplier. I keep getting an error on the first wait statement during analysis and elaboration : "wait statement must contain condition clause with until keyword" I have several working test benches written this way (i.e. signal assignment, wait for x ns, other assignment, wait for x ns ...). I can't seem to find what the error might be.

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY BoothMultiplier_32_test IS
END BoothMultiplier_32_test;

ARCHITECTURE test_arch OF BoothMultiplier_32 IS

SIGNAL A_test           :   STD_LOGIC_VECTOR (31 downto 0);
SIGNAL B_test           :   STD_LOGIC_VECTOR (31 downto 0);
SIGNAL result_test  :   STD_LOGIC_VECTOR (63 downto 0);

COMPONENT BoothMultiplier_32
    PORT (
        dataA, dataB    :   IN STD_LOGIC_VECTOR (31 downto 0);
        result          :   OUT STD_LOGIC_VECTOR (63 downto 0)
    );
END COMPONENT;

BEGIN
    DUT1: BoothMultiplier_32 
    PORT MAP(
        dataA=>A_test,
        dataB=>B_test,
        result=>result_test
    );

    testing : PROCESS
    BEGIN
        wait for 10 ns;
        A_test<=x"0000000A";
        B_test<=x"0000000A";
        --wait for 10 ns;
        --A_test<=x"10000000";
        --B_test<=x"00000010";
        --wait for 10 ns;
        --A_test<=x"FFFFFFFF";
        --B_test<=x"FFFFFFFF";
        wait;
    END PROCESS testing;

END ARCHITECTURE test_arch;

Unknown Unknown · Accepted Answer · 2015-02-14T02:42:29

The only observable error in your code is:

ARCHITECTURE test_arch OF BoothMultiplier_32 IS

Should be:

ARCHITECTURE test_arch OF BoothMultiplier_32_test IS

Preceding your entity and architecture pair with a dummy BoothMultiplier_32 and using the above correction:

library ieee;
use ieee.std_logic_1164.all;

entity boothmultiplier_32 is
    port (
        dataa, datab    :   in std_logic_vector (31 downto 0);
        result          :   out std_logic_vector (63 downto 0)
    );
end entity;

architecture foo of boothmultiplier_32 is
begin
end architecture;

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY BoothMultiplier_32_test IS
END BoothMultiplier_32_test;

ARCHITECTURE test_arch OF BoothMultiplier_32_test IS

SIGNAL A_test           :   STD_LOGIC_VECTOR (31 downto 0);
SIGNAL B_test           :   STD_LOGIC_VECTOR (31 downto 0);
SIGNAL result_test  :   STD_LOGIC_VECTOR (63 downto 0);

COMPONENT BoothMultiplier_32
    PORT (
        dataA, dataB    :   IN STD_LOGIC_VECTOR (31 downto 0);
        result          :   OUT STD_LOGIC_VECTOR (63 downto 0)
    );
END COMPONENT;

BEGIN
    DUT1: BoothMultiplier_32 
    PORT MAP(
        dataA=>A_test,
        dataB=>B_test,
        result=>result_test
    );

    testing : PROCESS
    BEGIN
        wait for 10 ns;
        A_test<=x"0000000A";
        B_test<=x"0000000A";
        --wait for 10 ns;
        --A_test<=x"10000000";
        --B_test<=x"00000010";
        --wait for 10 ns;
        --A_test<=x"FFFFFFFF";
        --B_test<=x"FFFFFFFF";
        wait;
    END PROCESS testing;

END ARCHITECTURE test_arch;

And the code then analyzes, elaborates and runs using the elaboration and run target boothMultiplier_32_test (while doing nothing interesting but none the less showing proper connectivity).

Perhaps you could tell us what tool you're having trouble with?

wait must contain condition clause with until keyword

1 Answers