ARM Instruction Set - Changing the CPSR (S bit)

Question

I was wondering why does not ARM Instructions set the CPSR by default (like x86), but the S bit must be used in these cases? When Instructions dont change the CPSR offer better performance? For example an ADD instruction offers better performance than ADDS? Or what is the real deal?

Answer 1

I was wondering why does not ARM Instructions set the CPSR by default (like x86), but the S bit must be used in these cases?

It is a choice and it depends on context. The extra flexibility is only limited by a programmers imagination.

When Instructions don't change the CPSR offer better performance? For example an ADD instruction offers better performance than ADDS?

Most likely never^Note1. Ie, an instruction that doesn't set CPSR does not execute faster (less clocks) for the majority of ARM CPUs and instructions.

Or what is the real deal?

Consider some 'C' code,

int i, sum;
char *p = array; /* passed in */

for(i = 0, sum = 0; i < 10 ; i++)
    sum += arrary[i];

return sum;

This can translate to,

 mov r2, r0          ; get "array" to R2
 mov r1, #10         ; counter (reverse direction)
 mov r0, #0          ; sum = 0
1:
 subs r1, #1         ; set conditions
 add  r0, [r2], #1   ; does not affect conditions.
 bne  1b
 bx   lr

In this case, the loop body is simple. However, if there are no conditionals with-in the loop, then a compiler (or assembler programmer) may schedule the loop decrement where ever they like and still set the conditions to be tested much later. This can be more important with more complex logic and where the CPU may have stalls due to data dependencies. It can also be important with conditional execution.

The optional 'S' is more a feature of many instructions than a single instruction.

Note1: Some one can always make an ARM CPU and do this. You would have to look at data sheets. I don't know of any CPU that take more time to set conditions.

Answer 2

It is for performance or perhaps was. if you always change flags then you have a hard time using one flag on multiple instructions without a branch which messes with your pipeline.

if(a==0)
{
  b=b+1;
  c=0;
}
else
{
  b=0;
  c=c+1;
}

traditionally you have to literally implement that with branches (pseudocode not real asm)

cmp a,0
bne  notzero
  add b,b,1
  mov c,0
  b waszero
notzero:
  mov b,0
  add c,c,1
waszero:

so you suffer a branch no matter what

but with conditional execution

cmp a,0
addeq b,b,1
moveq c,0
addne c,c,1
movne b,0

no branches you simply rip through the code, now the only way this can work is 1) you have an option per instruction to conditionally execute based on flags and 2) instructions that modify the flags have an option not to modify the flags

Depending on the processor family/architecture the add and maybe even mov will modify the flags, so you have to have both the conditional execution AND the option not to set flags. That is why arm has an adds and an add.

I think they got rid of all that with the 64 bit architecture so perhaps as interesting and cool as it was maybe it wasnt used enough or worth it or they just needed those four bits to keep all/some instructions to 32 bits.