How could I achieve DMA from a PCIe Verilog core?

4
votes

I have a PCIe generated core / endpoint with the xilinx core generator tool for a spartan6 fpga on a development board which I have modified a bit to enable MSI and send these every couple of seconds.

Also, I did a simple C kernel module on my linux desktop in which I plugged in the development board. This registers device, allocates memory, enables bus mastership for device and handles the interrupts etc.

What I want to do now is some DMA transfer from the board to the PC, and then will send an interrupt when finished, so that the cpu can go and read it. I'm not a Verilog expert, and the code I have doesn't seem to be capable of any DMA functions.

I couldn't find any relevant information online, so this is my last hope.

1
linux-kernelverilogdmapci-e
Have you implemented a transaction layer above the generated PCIe core? Why don't you use a free PCIe core if your HDL skills are not so high? PCIe is a very big thing.... – Paebbels
Thanks for this, I thought that is already done in the PIO since the Tx/Rx engine is there? I wasn't aware of the free PCIe cores mentioned; it would be great if you could point me to one that has TLP implemented since this version is the only free one I could get access to. – v1ctor23

1 Answers

3
votes

Original text from comment above:
Have you implemented a transaction layer above the generated PCIe core? Why don't you use a free PCIe core if your HDL skills are not so high? PCIe is a very big thing....

Yes, the Xilinx IPCore generator adds a very simple PIO interface ontop of the link layer to handle simple PIO transactioons. Note: PIO transaction are outdated and not allowed for new devices.

Currently I know two rather good IPCores:

  1. XILLYBUS

    • free educational license
    • create the IPCore for your FPGA device online and download a netlist
    • free linux and windows drivers (the linux driver will be included in the standard kernel)
    • 8-bit and 32-bit FIFO interface and a memory interface
    • linux-driver mapps FPGA to /dev/xillybus_read /dev/xillybus_write devices

  2. RIFFA

    • I'm not sure if this core is still maintained
    • free driver
    • it has a strange interface with up to 12 FIFO channels
    • free HDL sources

All these cores require the Xilinx Core Generator to generate a PCIe core for your device/board. The core itself provides transaction handling, ...