Class Object Instantiation in UVM

Question

In UVM Cookbook, it is written that class object instantiation is done at run time. But before run time, during compilation/elaboration also we may have all the details of class.

As depicted in the below image (Taken from UVM Cookbook), it is showed that Module and Interface instant creations are done in elaboration phase, but class object creation are done at run time.

enter image description here

Consider this sample example.

// Inside any .sv file
class A;
  int a;
endclass

A x;

initial
  x=new();

Now in this case there is no need of creating class at run time, as we have all the details of class available in compile/elaboration time like another module or interface details.

So why in Systemverilog, specifically only class instantiations are done at run time?

Even in C++ also object creation are not done at run time.

Note : In the question, I am talking about simple classes, not using inheritance, in which run time creation may become mandatory. By Creation I do not refer to memory allocation, as memory for all (module, interface, class) will be allocated during simulation only. I am just taking the context of the image.

Sorry to be so harsh, but you seem to have no idea about what you're talking about. Object creation is always done at run time, even in C++. Just because you compile the code that says "instantiate an object", it doesn't mean that that object is created at compile time. — Tudor Timi
@Tudor : Kindly check out the edited question, and let me know if you find any mistakes in my understanding or question itself. — Karan Shah

noobuntu noobuntu · Accepted Answer · 2016-10-31T20:42:22

All objects are created at run-time.

Maybe you are confusing run-time with run-phase? Run-phase is part of the phasing mechanism in uvm that allows for separation between different periods in a simulation. All uvm components can thus be synchronized by phase.

Object creation here is done in the build_phase, which is part of the run-time.

Class Object Instantiation in UVM

2 Answers