Clock period in Verilog HDL always block

Question

This is from Cavanagh's Verilog HDL: Digital Design and Modeling.

//clock generation using initial and always statements

module clk_gen2 (clk);

output clk;
reg clk;

//initialize clock to 0
initial
    clk = 1'b0;

//toggle clock every 10 time units
always
    #10 clk =~ clk;

//determine length of simulation
initial
    #100 $finish;

endmodule

A part of its explanation says that

[...] the always statement cycles the clock every 10 time units for a clock period of 20 time units.

I got lost at 20 time units. Where did that come from?

Answer 1

It requires two toggles of the clock to generate one period.

Answer 2

That always block changes the clock signal status (high to low and low to high) every 10 time units. If the clock changes each 10 time units, it's period would be 20 time units e.g clock changes every 10 seconds, it's half cycle would be 10 seconds and its period would be 20 seconds.