'last_event VHDL equivalent in verilog

0
votes

I'm searching the verilog equivalent of the VHDL attribute my_signal'last_eventbut in Verilog. I have googled it without success. Does someone know how to do it ?

The 'last_event attribute is used to know the time since the signal last event. For example, if at time 15us, signal toto toogles from 0 to 1. Then at time 20us, toto'last_event returns 5us.

2
vhdlverilog
When trying to translate from one language to another, it usually helps to have a bigger picture of what you are trying to do. For example, Verilog has built-in timing checks that VHDL does not have that might eliminate the need to do this. - dave_59
@dave_59, Yes I have understood that the way I used to write my tests in VHDL is not efficient for verilog. And I've changed this very test to avoid searching for the last event time. - grorel
@dave_59, Are the "Verilog built-in timing check" functions these one ? - grorel

2 Answers

0
votes

Have you tried looking into some of the verilog system tasks? Specifically the following:

$time;                            // Return current simulation time in 64-bit integer 

$monitor("format", v1, v2, ...);  // Invoke only once, and execute (
                                  //   automatically when any of the
                                  //   variables change value.

You can look at the 'nested-if-else-if' example here http://www.asic-world.com/verilog/vbehave2.html for an example of a test bench that uses these.

0
votes

You could create a time variable and update it whenever the signal changes

time my_signal_last_change;

always @(my_signal) begin
    my_signal_last_change = $time;
end

This works in SystemVerilog; not sure if it would in verilog (you can try changing time to reg[63:0] in case it doesn't)