Computer Architecture: Cache Transfer Analysis

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This is a question on my exam study guide and we have not yet covered how to calculate data transfer. Any help would be greatly appreciated.

Given is an 8 way set associative level 2 data cache with a capacity of 2 MByte (1MByte = 2^20 Byte) and a block size 128 Bytes. The cache is connected to the main memory by a shared 32 bit address and data bus. The cache and the RISC-CPU are connected by a separated address and data bus, each with a width of 32 bit. The CPU is executing a load word instruction

a) How much user data is transferred from the main memory to the cache in case of a cache miss?

b) How much user data is transferred from the cache to the CPU in case of a cache miss?

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cachingcomputer-architecturedata-transfer
Your question doesnt related to programming and doesnt show any search efford. - mrgenco
@mrgenco It relates to low-level programming, namely computer-architecture. And as far as search effort goes, I've spent the last 8 hours reading through my book trying to figure out how to do this. I cannot find this info in my book though; this is a question my prof. made up. Therefore, I am asking for help. - user4278114
Tell us what do you think and why and we will tell you if you are right :) - VAndrei
@VAndrei It was due earlier, but I honestly had no clue how to do this. I said: For A, since there are 8 blocks of 128 bytes that need to be updated, 8*128 = 1024 bytes will be transferred from the memory. For B, there are two buses of 32 bits, 64 bits are sent first, then the miss is declared, so after the miss is resolved from the memory, the instruction has to resend another 64 bits to the CPU, totaling in 128 bits. However, that is just from simplistic logic of how I understand this (and I don't understand this at all); it was just my best guess because I couldn't just leave it blank. - user4278114

1 Answers

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You need to compute first your cache line size:

  1. Number of cache blocks: 2MB / 128B = 16384 blocks (14 bits)
  2. Number of sets: 16384 / 8 way = 2048 sets (11 bits)
  3. Address width: 32 bits
  4. Line offset bits: 32 - 14 - 11 = 7 bits

So the cache line size is 128B - actually a line is a block but it's good to know the above computation.

a) How much user data is transferred from the main memory to the cache in case of a cache miss?

In your problem, the L2 cache is the last level cache before main memory. So if you miss in the L2 cache (you don't find the line you are looking for), you need to fetch the line from main memory. So 128B of user data will be transferred from the main memory. The fact that the address bus and data bus are shared does not influence.

b) How much user data is transferred from the cache to the CPU in case of a cache miss?

If you reached the L2 cache that means you missed the L1 cache. So from L2 the CPU has to transfer to L1 a full L1 cache line. So the L1 line size is 128B, then 128B of data will go from L2 to L1. The CPU will use then only a fraction of that line to feed the instruction that generated the miss into the L1 cache. Whether that line is evicted or not from L2, this should have been stated in the problem sentence (inclusive / exclusive cache)