Your data will not be corrupted - these chips have bus arbiter that grants access to bus (so also to RAM memory) to either DMA or the CPU (your code), so each transaction (single access to RAM, not necessarily access to whole variable) is atomic.
See this info in the RM0008 Reference manual:
3.1 System architecture
...
BusMatrix
The BusMatrix manages the access arbitration between the
core system bus and the DMA master bus. The arbitration uses a Round
Robin algorithm. In connectivity line devices, the BusMatrix is
composed of five masters (CPU DCode, System bus, Ethernet DMA, DMA1
and DMA2 bus) and three slaves (FLITF, SRAM and AHB2APB bridges). In
other devices, the BusMatrix is composed of four masters (CPU DCode,
System bus, DMA1 bus and DMA2 bus) and four slaves (FLITF, SRAM, FSMC
and AHB2APB bridges). AHB peripherals are connected on system bus
through a BusMatrix to allow DMA access.