ARM MMU, handle L2 page table

Question

How can we determine the base address of the L2 page table? (Using ARM Cortex-A9)

For example, if I have a programme which requires 7KB of data space and starts at the address 0x0, I need two pages of 4KB. To do that, I add an entry in the L1 page table which points to the L2 page table base address. Then I add two entries in the L2 page table like that (with addr = 0x0 for the first page and 0x1000 for the second one)

u32 *ptr;
u32 small_page;

small_page = addr / 0x1000;
ptr        = small_page + L2_table_base_addr;
*ptr       = (addr & 0xFFFFF) | attributes;

Now there is one thing that I still do not understand. How can I determine the L2 page table base address? Should I put the table right after the L1 page table?

Where can I store the address? I know that the base address of the L1 page table is stored in a coprocessor register but I did not find any register to store the L2 base address.

Another question to be sure, both coprocessor register TTBR0 and TTBR1 holds the base address of a L1 page. Each to its own. It is not TTBR0 for L1 and TTBR1 for L2, does it ?

But... you've already stated the answer before asking the question - the addresses of L2 page tables are stored in the entries of the relevant L1 table. As for where in physical memory they actually reside, you can put them wherever you want. — Notlikethat
Ok, I see now where I was wrong. I thought there was a table of L2 page tables. — Olivier
There are lots of questions and answers here which would provide this information. For example, What is the right way to update MMU translation table. You could pick one that answers your question and click close and select that answer as a duplicate. See: arm+mmu search for possible candidates. This will help future readers (like you) find an answer. Note, all tables have alignment restrictions. — artless noise

Ganesh Kalbhor Ganesh Kalbhor · Accepted Answer · 2015-04-16T01:02:37

I would recommend to read Chapter 9 Memory Management Unit of the Cortex-A Series Programmers Guide. There you will find clear explanation about base address storage. The base address of Level 1 TTB is stored in one of the two base registers (TTRB 0/1 depending upon whether table locates OS code or user process code). These two base registers are helpful while context switching.

The address of the L2 translation table entry that required is calculated by taking the (1KB aligned) base address of the level 2 translation table (given by the level 1 translation table entry) and using 8 bits of the virtual address (bits [19:12]) to index within the 256 entries in the L2 translation table (256 because its 4 byte per index so total bytes are 256*4bytes=1KB).

ARM MMU, handle L2 page table

1 Answers