How to pass values between modules in verilog?

Question

I am taking a hardware class and we are supposed to do a huge project using Verilog with out much instruction but we were told that it is very similar to C. In some way it may be so, but in others not at all. For example, I spent a couple of hours looking online at how to pass variables between modules and wasn't able to figure it out. So Starting from startMod I am trying to call dispBinHex to display the binary number that was selected using addition between sw[3:2] and sw[2:1] switches on the Altera board on the hex display. But I keep getting all kinds of errors, I tried many different things to get around this, but no luck. The most common error is "heierchy cannot be resolved" and with the code below I get "output or inout port 'out' must be connected to a structural net expression". I found some articles online about connecting modules by name or by position, and that part is still beyond me. I am completely at a loss on how to do even the basic modules parameter passing with Verilog and thinking about dropping this class, could someone shed some light on how to use modules as we do functions in C. The following code is all in one file named startMod and it has to be a synthesizable subset of Verilog. Here's what I have:

module dispBinHex (select, out);
 //Edit: changed input from [3:0] to [1:0]   
      input [1:0] select;
      output reg [6:0] out;

      always @(select)
      begin
        out = 7'b1000000;
          case (select)
            4'b0000: out = 7'b1000000;  // 0
            4'b0001: out = 7'b1111001;  // 1
            4'b0010: out = 7'b0100100;  // 2
          endcase 
      end
    endmodule

    module startMod( 
    input [9:0] sw,
    input [3:0] key, 
    input clock,
    output [9:0] ledr, 
    output [7:0] ledg, 
    output reg [6:0] hex
    );

    integer i;
    reg [3:0] switch;
    switch = sw[3:2] + sw[2:1]; 

/*
    Edit: I replaced the code below until ***********************     
        if (sw[0] == 1'b0)
                begin
                    case (switch)
                        4'b0000:
                            begin
                                dispBinHex BH(.select(switch), .out(hex0)); 
                            end
                        4'b0001: 
                            begin
                                dispBinHex BH(.select(switch), .out(hex0)); 
                            end
                        4'b0010: 
                            begin
                                dispBinHex BH(.select(switch), .out(hex0)); 
                            end
                        4'b0010: 
                            begin
                                dispBinHex BH(.select(switch), .out(hex0));                     
                            end
                  endcase
              end
    ***************************************************
*/
    // with this code

              reg [1:0] switch;

              if (sw[0] == 1'b0)
              begin
                  switch = sw[4:3]+sw[2:1];
                   dispBinHex BH(.select(switch), .out(hex0));
              end
        endmodule

But the error message I get now is:

Error (10170): Verilog HDL syntax error at L2C227.v(73) near text "BH";  expecting "<=", or "="

Please post the errors you get. Also, post the warnings from synthesis only (because compiling gives you hundreds of ignorable warnings) — Noobification

Morgan Morgan · Accepted Answer · 2014-10-28T08:18:11

I would recommend you read Verilog in a day. As verilog is not like C, some syntax is the same but the way the language works is not. It is after all a hardware description language.

Variables are not passed between modules, you describe wires that would physically connect them.

When you get to the section on Control Statments they look alot like C but they must be contained in a block. You can have:

always @(posedge clk) // Describes a flip-flop behaviour
always @*             // Describes combinatorial hardware

You can also have initial which is useful for testbenches as it is only run once at the start.

From this you should see that you can not have floating case or if statements. At present you have if (sw[0] == 1'b0) not contained in a block.

How to pass values between modules in verilog?

2 Answers