Altera Quartus and modelsim

Question

I am writing something in verilog in quartus, and appeared to me something strange, but pretty simple actually

This code increments the address correctly

    module counter(
    input wire clock,
    input wire reset,
    output reg [4:0]address
);

initial
begin
    address = 5'b0
end

always@(posedge clock)
begin
    if(reset)
    begin
        address <= 5'b0;
    end
    else
    begin
        address <= address + 5'b00001;
    end
end

endmodule

this, the bits that change become not matter, it happens when I start the output to something other than 0

module counter(
    input wire clock,
    input wire reset,
    output reg [4:0]address
);

initial
begin
    address = 5'b11101;
end

always@(posedge clock)
begin
    if(reset)
    begin
        address <= 5'b0;
    end
    else
    begin
        address <= address + 5'b00001;
    end
end

endmodule

Does anyone know any way to solve this problem?

Answer 1

While it is difficult to tell exactly what you are saying, it seems you are curious as to why changing the starting value in the initial block seems to have no affect on where the counter starts.

It seems you are likely performing a reset as part of your testbench, so when you look at address, the value always starts at 0 (because the initial block setting is changed by the reset in the always block).

Answer 2

This part is suspicious to me:

if(reset)
begin
    address <= 5'b0;
end

Should be:

if(reset)
begin
    address <= 5'b00000;
end

You can try use this implementation with load and start signal:

 module Counter(load,clk,start,data_in,data_out);
    input load;
    input clk;
    input start;
    input [5-1:0] data_in;
    output [5-1:0] data_out;
    reg [5-1:0] tmp;
    initial
    begin
        tmp = 5'b0000;
    end
    always @ ( posedge clk)
        begin
        if(~start)
        begin
            tmp <= 5'b0000;
        end
        else if(load)
            tmp <= data_in;
        else
            tmp <= tmp + 1'b1;
    end
    assign data_out = tmp;
endmodule