How to simulate PCIe to debug my fpga endpoint

1
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Im working on an fpga controller connected through pcie. The only way i can debug the hardware is using chipscope. So i execute commands through my driver and check out the signals from the fpga.

The problem is that it takes a lot of time to build the project and load it to the fpga every time i want to check a signal to debug the project.

Is there an easier way to debug an fpga connected to pcie?

Is there a way i can simulate all the pcie signals and not have to run the fpga at all?

2
verilogfpgaxilinxpci-ehardware-programming
I think this should be moved to ElectronicsSE as it is mainly about debugging hardware. – Morgan
Search for "PCIe BFM" (Bus Functional Model). This is what you use when you want to simulate one side of a bus protocol. I don't know if you'll find one, but something may be out there. – Tim
What layer of PCIe are you implementing? Many FPGAs have hard IP cores and expose streaming interfaces for TLPs... – Chiggs
@Morgan the question is actually asking how to move away from hardware and debug in simulation, which has historically been an acceptable topic for SE. – Chiggs
@chiggs, that is not how I understood the question, I was focusing on this line Is there an easier way to debug an fpga connected to pcie but I think the OP really just wanted to debug the design. – Morgan

2 Answers

0
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One thing you can do is to capture a trace of the PCIe transactions into a buffer, then read that out and replay it as the stimulus in a testbench during simulation.

You can use a BRAM or possibly FPGA-attached DRAM for the buffer.

You will probably need an alternate path for reading out the buffer. Xilinx has a JTAG to AXI master that you could use to read out the buffer. Or if your PCIe is stable you can read it out that way.

0
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As mentioned in several comments, you want to do detailed debugging in simulation rather than in hardware. The loop time to debug via chipscope, determine the problem, come up with a new set of signals to probe, recompile, and push new code into the FPGA. This is a very painful process compared to debug in simulation.

If you are trying to debug PCIe, you can either get a PCIe BFM from a commercial vendor or possibly off of OpenCores, or you can use the capture buffer described.

If you are trying to debug your own logic and PCIe only comes in because that is the interface to the device, you are best off writing your own BFM that drives transactions to your internal logic as if it were the PCIe core. Reproduce the problem in sim, debug there, then go back to the FPGA once you have good code coverage and a decent suite of passing tests.