how is the communication of PCIe using BAR defined?

1
votes

I'm a total beginner in PCIe and have to develop a simple PCIe driver.

If I do have a PCIe device with a memory of 1kByte, what does the BAR contain? The addresses for the 1kByte space? And what does it mean that the BAR is "mapped" into the memory or i/o address space?

Tried to find the answers in different books, without success...

Best regards Thomas

1
pci-e
What language are you using to write said driver? What system are you using? What have you tried? – gabeio
I'm using C. Ubuntu 12.04 LTS Well I've tried to get an inside view by reading ldd3 and another linux driver book. I began developing the driver, but I don't understand the principle about the whole addressing in PCIe. If I want to read a register out of my PCIe device (in my case a FPGA), which address do I use? What is the BAR for? – Thomas

1 Answers

1
votes

The BAR will initially contain the type of the requested memory (bit 0 - MEM or IO) if it's a MEM bar you'll need to choose if it's a 32b or 64b region bar and also if it corresponds to a prefetch able (cachable) region. These attributes occupies the 4 LSBs or the BAR. The rest of the bar is for the requested size for allocation , the size that your device requests for allocation (bit for byte) should be read-only bits with value of 0. For example, a 1 kb memory would have to be represented in the bar that have bits 4-9 read only values set to 0. Bits 3-0 will have the attributes.