Non-Thumb ARM code on Cortex M3

Question

I've got some ARM code that I'm trying to run on the Cortex M3. The majority of my code in written in Thumb, compiled from C - but for some functions I'd like to be able to run normal ARM code (as I understand it, this is possible on the M3?).

So...

Original C code and assembly:

int donothing(int a) {
  return a;
}


00000068 <donothing>:
  68:   e52db004    push    {fp}        ; (str fp, [sp, #-4]!)
  6c:   e28db000    add fp, sp, #0
  70:   e24dd00c    sub sp, sp, #12
  74:   e50b0008    str r0, [fp, #-8]
  78:   e51b3008    ldr r3, [fp, #-8]
  7c:   e1a00003    mov r0, r3
  80:   e28bd000    add sp, fp, #0
  84:   e8bd0800    ldmfd   sp!, {fp}
  88:   e12fff1e    bx  lr

Compiled using arm-none-eabi-gcc -mfloat-abi=soft -nostdinc -nostdlib

I branch to this with blx r4 - which should exchange if the base address&3 is 0, which it is.

Stepping through this in GDB, it HardFaults as soon as it gets to the line shown, even though the address contains the right data.

(gdb) p/x *0x2000934c 
$2 = 0xe52db004

The code (with BLX) works perfectly for Thumb code though...

Any idea what's going on? Thanks!

The M3 doesn't have an ARM mode. It supports the Thumb-2 instruction set, which includes some 32-bit instructions (see e.g. arm.com/files/pdf/Cortex-M3_programming_for_ARM7_developers.pdf) — Michael
That advice applies to the whole Cortex-M series. The particular instruction supported by each Cortex-M variation is given there. The are all Thumb/Thumb2; Ie, they execute with CPSR bit 5 is set. — artless noise
The obvious question is why? Thumb-2 covers all but the more esoteric corners of the ARM ISA - most ARM assembly code should convert with minimal tweaking unless you're overusing conditional execution (which would be sub-optimal even in ARM mode on modern cores). For compiled code, instruction set should be a non-issue. Admittedly the M3 is a subset of Thumb-2, but it's only really the DSP stuff that's missing. — Notlikethat
the cortex-m0 and -m1 are armv6m which has only a dozen or two thumb2 extensions, the cortex-m3 and -m4 are armv7m which has about 150 thumb2 extensions, so be careful trying to lump the two together when comparing thumb2 to arm. — old_timer

Variable Length Coder Variable Length Coder · Accepted Answer · 2014-04-10T20:47:31

Cortex-M processors do not support ARM mode instructions. They only support Thumb-2, which includes a mixture of 16 and 32-bit instructions. There is no way to run ARM instructions on a Cortex-M.

Non-Thumb ARM code on Cortex M3

1 Answers