Verilog Combinational Logic

Question

I'm attempting to implement the following logic equation in Verilog:

A1'*B1 + A1'*A0'*B0 + A0'*B1*B0

where A1, A0, B1, B0 are inputs and ' indicates negation. This is my first go at coding in Verilog, and I'd like to see if I'm on the right track. Any help would be much appreciated.

This is what I have worked up:

1 module HW7P1( A1, A0, B1, B0, O )
2      input A1, A0, B1, B0
3      output reg O;
4     
5      always @( A1 or A0 or B1 or B0 )
6      begin
7          if( !A1 && B1 ) begin
8              O <= 1;
9      end else if( !A1 && !A0 && B0 ) begin
10             O <= 1;
11     end else if( !A0 && B1 && B0 ) begin
12             O <= 1;
13     end else begin
14             O <= 0;
15     end
16     end

Have I done anything wrong here?

toolic toolic · Accepted Answer · 2014-03-25T17:48:51

I believe the following continuous assignment is equivalent to your logic equation:

wire O = (!A1&B1) | (!A1&A0!&B0) | (!A0&B1&B0);

You should create a testbench to prove that this is the logic you desire.

Verilog Combinational Logic

1 Answers