4
votes

For example, in the standards C11 and C++11, features 6 types of memory barriers: http://en.cppreference.com/w/cpp/atomic/memory_order

  • memory_order_relaxed
  • memory_order_consume
  • memory_order_acquire
  • memory_order_release
  • memory_order_acq_rel
  • memory_order_seq_cst

Which are determine the directions in which the compiler can reorder instructions, as well as which of processor instructions requires to insert to limit reordering in pipeline of processor. For example, the first five barriers affect only the compiler , but does not generate any CPU instructions (no S/L/ MFENCE), because in x86 - acquire-release-semantics is provided automatically .

How many types of memory barriers available in Java? Or is there only 2 types?

  • All reordering allowed
  • All reordering prohibited
1
Try informing yourself on the Roach Motel model, which covers your question for the most part.Marko Topolnik
C++11 has only two barriers, "thread fence" and "signal fence". However, those are configurable with memory ordering parameters.Kerrek SB
@Kerrek SB I mean - memory_order, which can be used in "thread fence", "signal fence" or "atomic variable".Alex
The Java memory model is part of the Java specification.Kerrek SB
@Alex "memory_order, which can be used in "thread fence", "signal fence"" Only some of these values make sense for fences: only the directions (acq and rel) make sense for a signal fence; in addition, seq_cst makes sense for a thread fence. The others only make sense for an operation on atomic.curiousguy

1 Answers

5
votes

There are no explicitly specified "memory barriers" in spec of Java language or its standard libs. There is a Java Memory Model (JMM) which bases on "happens before" relationship. Of course, an implementation of JVM uses some memory barriers to implement JMM, but they are implementaion/hardware specific. See for instance: http://gee.cs.oswego.edu/dl/jmm/cookbook.html That article defines LoadLoad, LoadStore, StoreLoad, StoreStore abstract memory barriers (non-standard really, but widely used terminology) and describes how they can be implemented on specific hardware.