Generate frequency on FPGA

Question

I'm looking to generate a small signal from my FPGA. I'd like to output it through the stereo out on my board. The latter would act as a simple DAC. The following is a simple Verilog program that should play a beep but does not.

module music(clk, speaker);

input clk;
output speaker;

// Binary counter, 16-bits wide
reg [15:0] counter;

 initial 
    begin
    counter = 0;
    end

always @(posedge clk) counter <= counter+1;

// Use the most significant bit (MSB) of the counter to drive the speaker
assign speaker = counter[15];
endmodule

Ultimately I'd like to output a very low frequency sinusoidal wave through the stereo out. Is there any example code on how to do this...any ideas? I'm using a DE2i-150 board. Thanks!

isn't that what "reg[15:0] counter;" does? Can you please provide the code. — user2402616
What is the clock frequency? Is the output waveform something in the audible spectrum? — Tim
The clock frequency is at 25MHz and the output should be a square signal around 380 HZ. — user2402616

Ari Ari · Accepted Answer · 2014-02-25T21:58:57

I would use an async reset for initializing the counter:

module music(clk, _reset, speaker);

input clk, _reset;
output speaker;

// Binary counter, 16-bits wide
reg [15:0] counter;

always @(posedge clk or negedge _reset) 
    if (_reset == 1'b0)
        counter <= 'b0;
    else 
        counter <= counter + 1;

// Use the most significant bit (MSB) of the counter to drive the speaker
assign speaker = counter[15];

endmodule

testbench on edaplayground.

You can play with clock frequency and the upper limit of the counter to get the frequency that you want, i.e., rather than using the most significant bit, just write:

if (counter == UPPER_LIMIT) begin speaker = ~speaker; counter <=0; end

This only generates a square wave. In order to generate a sine wave, one easy way is to create a look-up table. See this.

Generate frequency on FPGA

1 Answers