1
votes

Currently i have a requirement to support MSI with 2 vectors on my PCI device. Each vector needs to have a different handler routine. HW document says the following

vector 0 is for temperature sensor

vector 1 is for power sensor

Below is the driver code i am following. 1. First enable two vectors using pci_enable_msi_block(pdev, 2) 2. Next assign interrupt handlers using request_irq(two different irq, two diff interrupt handlers).

int vecs = 2;
struct pci_dev *pdev = dev->pci_dev;
result = pci_enable_msi_block(pdev, vecs);

Here result is zero which says call succeeded in enabling two vectors.

Questions i have is:

  1. HW document says vector 0, i hope this is not the vector 0 of OS right? In any case i can't get vector 0 in OS.
  2. Difficult problem i am facing is when i do request_irq() for first irq, how do i say to OS that i need to map this request to vector 0 of HW? Consecutively for second irq, how do i map t vector 1 of HW?
2

2 Answers

2
votes

pci_enable_msi_block:

If 2 MSI messages are requested using this function and if the function call returns 0, then 2 MSI messages are allocated for the device and pdev->irq is updated to the lowest of the interrupts assigned to the device.

So pdev->irq and pdev->irq+1 are the new interrupts assigned to the device. You can now register two interrupt handlers:

request_irq(pdev->irq, handler1, ...)  
request_irq(pdev->irq+1, handler2, ...)
0
votes

With MSI and MSI-X, the interrupt number(irq) is a CPU "vector". Message signaled interrupts allow the device to write a small amount of data to a special memory-mapped I/O address; the chipset then delivers the corresponding interrupt to a processor.

May be there are two different MSI interrupt data that can be written to a MSI address. Its like your hardware supports 2 MSI (one for Temperature Sensor and one for Power Sensor). So when you issue pci_enable_msi_block(pdev, 2);, the interrupt will be asserted by the chipset to the processor whenever any of the two MSI data is written to that special memory-mapped I/O address (MSI address). After the call to pci_enable_msi_block(pdev, 2); ,you can request two irqs through request_irq(pdev->irq, handler, flags....) and request_irq(pdev->irq + 1, handler, flags....). So whenever the MSI data is written to the MSI address, pdev->irq or pdev->irq + 1 will be asserted depending on which sensor sent the MSI and the corresponding handler will be invoked.

This two MSI data can be configured into the hardware's MSI data register.