I using a Cortex-M4 in a STM32F4 board, developing in a Keil uVision5 and
I am trying to count the exact number of reads and writes performed by the CPU in the memory RAM. Including loads, stores and fetched instructions. With the help of instruction set simulator I can calculate the number of load/stores and executed instructions, however I need to make sure that is a good approximation.
I am aware of the DTW registers, but they don't have enough information.
1
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unless ARM has logic for this which I doubt, then it will be a mostly impossible task. the memory accesses, the instruction fetches, the speed of the memory and flash, etc are all going to both interfere and act in parallel in a way that you cant isolate anything. Maybe if you can get the whole of the software in the cache at once the fetches are there but faster and the memory accesses will dominate the time of execution, compare that to the same thing with the cache off and you can at least measure the fetch time.
– old_timer
Thank you. I've searched in the architecture and found a few cycles related register, but not really useful. I was hoping that someone knew functions provides by debugers like JTAG or SWD.
– frdarosa
1 Answers
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Cortex-M4 has only the DWT registers which can provide some limited performance information. There is no equivalent to the PMU (performance monitor unit) which might provide the information you're looking for in a larger core. Still, you're more likely to see a count of executed instructions rather than fetches on the instruction interface.
You can use ETM trace to confirm the sequence that you see in simulation (if there are real-time events which might make simulation inaccurate), but this will only provide the same 'executed instruction' view.
