Endianness conversion cost on architectures

Question

Today there are two kinds of CPU architectrues, big endian and little endian. So data needs to be converted between the two representations. Each CPU architecture, instruction set in particular, is different and each allows for different implementations for changing endianness. Some CPUs contain specific instructions while others do not.

My question is this, with today's architectures is it more efficient to have data BE and convert on LE architectures or other way around, in order to minimize data conversion latency and thus maximize throughput in a BE to LE communication.

Second question, can the cost of conversion quantified, is there any data on the matter?

How costly is this conversion in Java from a byte array? Is there data on specific JVMs on specific architectures? Is it different on Dalvik?

AFAIK the relevant architectures for this would be x64, ARM, MIPS and JVM/Dalvik. Am I missing any?

If I get it right you want to choose the endianness of the exchangeable data in order to put the hard work on one or the other platform (for example in case of network communication)... I'm not an expert in the area but I have a bit of doubt that this can not be answered clearly. For example ARM itself is just a licensable thingy and if you buy the license you can implement/modify/customize the processor as you wish and you can build it together with whatever other hardware that can have huge effect on the overall performance for different tasks. You have to measure concrete target platforms. — pasztorpisti
@pasztorpisti you're correct in all observations, but there still are only a limited number of platforms, even with customizations so the problem can be quantified. I think it's especially interesting in case of interpreted languages and JITs. — Martin
Even if we talk only about iPads as an example we are already talking about a relatively large hardware family with some versions having totally different characteristics and this family just grows every year. If we wanted to talk about every popular hardware we currently have in popular mobile devices... :-) But I'm also curious whether someone has an answer to this question. — pasztorpisti
@pasztorpisti Do you know if there's much variation in the CPU microarchitecture in iPads? AFAIK Apple has their own version of the CPU, but I doubt they tweak every bit it. I don't say they've made no changes, but treating every small variation as a special case is an overkill. The same variation exists in x64, AMD has different latencies from Intel (and i5 differs from i7, etc, I've even found some bugs [edge cases]), but there's still some quantification that can be done for the platform as a whole. So, just like there's data on context switch cost, I think this is doable too. — Martin
I'm rather a software developer not a hardware expert but as far as I know Apple has simply designed its own arm-compatible processor for iPhone5 and iPad4. With these new phone/tablet versions the performance gain was quite impressive compared to the previous versions (benchmarking with C code) but I can't comment for example on how have they changed the performance - power consumption balance... — pasztorpisti

phuclv phuclv · Accepted Answer · 2014-02-01T01:47:02

Storing data is one of the most basic things computers do, why only a few architectures relevant? All architectures must follow a specific endianness (such as x86/x86_64) or bi-endian (ARM, MIPS...) if their word size is bigger than an octet

However even if the architecture is bi-endian, the endian must be set at startup and CPUs only work in that endian mode until the mode is changed and everything is restarted. The CPUs can't deal with data in the reversed endian. Therefore data should always be in the native endian unless you only copy the value and then send it back without any processing, or you do some very simple operations that are endian-agnostic like bitwise operations

Network activities are much slower than CPU, not even comparable to RAM speed. You'll hardly ever see any difference in speed but most likely will be memory bound

Endianness conversion cost on architectures

1 Answers