Driving input signals combinatorially (in the same cycle) in UVM

Question

If I want to combinatorially drive a design input signal based on certain output from the design in UVM driver, what is the best way? If I implement it in run phase and look at the design output signal, I will see it on next positive edge of clock, right? This will waste a cycle.

E.g. rd input signal is asserted randomly to design; except when empty is high, it should de-assert in the same cycle.

Tudor Timi Tudor Timi · Accepted Answer · 2014-01-29T09:00:10

Implementing anything in the run phase does not automatically mean that you will synchronize on the posedge of the clock. You can always fork out a method from the run phase that waits for a change in a specific signal and then does something at that point:

task run_phase(uvm_phase phase);
  fork
    monitor_comb_sig();
  join_none
endtask

task monitor_comb_sig();
  forever begin
    @(some_signal); // waits until some_signal changes

    // drive some other signal based on this change
  end
endtask

Driving input signals combinatorially (in the same cycle) in UVM

1 Answers