ModelSim Compiler not the same as Quartus

Question

I was using ModelSim to do the simulation these days, and a problem came to me, that is:

And thers was a piece of verilog code like this:

if (cnt == `END_CNT)
...
reg [7:0] cnt;
always @(posedge clk)
    if (en)
        cnt <= cnt +1;
...

which means I define the reg right up to the assigning block, and I may use the variable before definition. It is my coding style and it works all right in Quartus.

But when I compiled the file in ModelSim, a "variables undefined " error would come, and I have to move the definition line above if statement:

reg [7:0] cnt;
...
if (cnt == `END_CNT)
...
always @(posedge clk)
    if (en)
        cnt <= cnt +1;
...

I have a lot of code like this, and it bothers me so much. As a ModelSim beginner, I am wondering is there a compiler setting( I can not find any) to deal with my problem?

In my experience, Modelsim is the strictest simulator with respect to enforcing language laws. @toolic You should make your comment an answer. — dwikle
@dwikle, so I guess there is no such a setting then, thank you anyway. — Mr.Zhou
If you put `default_nettype none at the top of your source then quartus will also complain about your code, so you will get consistent behaviour. — Will
Don't forget to reset the defaut net type mode to wire afterwards, using `default_nettype wire . More details on implicit net types here: sunburst-design.com/papers/… — rascob

mohsaied mohsaied · Accepted Answer · 2014-12-07T21:26:36

The Quartus verilog compiler is not as strict as the modelsim one, so it will allow you to do some funny things like the one you mentioned.

However, according to the Verilog standard, regs may only be used after they are declared so the only way around this is to move your reg declarations before their use.

reference: SystemVerilog Standard (see section 6.5: Nets and Variables) http://standards.ieee.org/findstds/standard/1800-2012.html

ModelSim Compiler not the same as Quartus

1 Answers