Is there a hardware buffer in SPI module?

1
votes

I am using a SAM4E-EK board, and the processor is SAM4E. The board is equiped with a ADS7843 touch controller, contected from the processor through a SPI channel.

The chapter of SPI in datasheet of SAM4E said that

While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Receiving data cannot occur without transmitting data.

But in an example for ADS7843 from ASF, it just sends data(8 bits) three times at first, and then it can receives data(8 bits) three times! I have test it, and it work fine.

So I think there is a hardware FIFO buffer in SPI receiver. But I can not find any related information in the datasheet and internet.

Am I right? or is there others mechanism making the example runs correctly?

1
spicortex-m
Could be that it is ignoring the received data bytes for the first 3 transmitted bytes. But is highly unlikely that this is the case because of this sentence Receiving data cannot occur without transmitting data. I too think there should be Fifo buffers in hardware for Tx and Rx. Look-up the SPI module registers. – Uchia Itachi

1 Answers

0
votes

The SAM4E manual says that SPI Receive Data Register has the size of 2 bytes

The ADS7843 manual says:

One complete conversion can be accomplished with three serial communications, for a total of 24 clock cycles on the DCLK input

The figure 5 shows that byte0 is a request to ADS7843 and bytes1-2 are response.

You should send 1 byte of command and 2 dump bytes to provide SPI clocking while the ADS7843 is responsing (the manual says

Receiving data cannot occur without transmitting data

And when you reading 3 bytes, you get the 2 bytes of answer, stored in the SPI Receiver register