system verilog assertion trigger==1 4 cycles before signal asserted

Question

How would I write SVA that checks that if sig goes high trigger was high 4 cycles before trigger [*4] |-> signal is not good enough because it does not check that signal didn't go high for 3 cycles. Should I use $past how ??

Answer 1

This would check that on a rising edge of sig, trigger was high 4 clk cycles ago:

assert_name: assert property (
   @(posedge clk) (
     ($rose(sig) -> $past(trigger,4))
   )
);

Answer 2

There's nothing stopping you writing a small piece of synthesisable RTL which counts how many cycles trigger has been high.

always @(posedge clk) begin
    if (trigger) begin
        triggerCount := triggerCount + 1;
    end else begin
        triggerCount := 0;
    end
end

assert_name: assert property (
   @(posedge clk) (
     ($rose(sig) -> triggerCount == 4)
   )
);