VHDL - Asynchronous up/down counter

Question

I'm doing a college's task that asks for implementing in VHDL an up/down asynchronous counter.

My implementation consistis of using a control variable ctrl so when it's 0, the counter counts in ascendant order, else in descendent one.

The code I've implemented (In the discipline, we use Quartus 13 and FPGA Cyclone IVE EP4CE129C7 for simulation) is followed in this link. The resulting simulation, however, exhibits only '0' for outputs q0 and q1.

So, where can be a possible bottleneck in the code so that this is occuring?

Unknown Unknown · Accepted Answer · 2013-10-21T04:13:12

I'm not a quartus user so have no familiarity with the limits of your waveform viewer, but this looks like it's caused from migrating from type BIT to type Std_Logic. Where the default value (unless otherwise specified would be 'U' for Std_Logic (Std_ULogic) while it would be '0' for type BIT.

That results in you assigning NOT 'U' for the FFT q's to the input of the MUX. The result is your flip flops never get assigned a value other than 'U'.

From the std_logic_1164 package:

   -- truth table for "not" function
    CONSTANT not_table: stdlogic_1d :=
    --  -------------------------------------------------
    --  |   U    X    0    1    Z    W    L    H    -   |
    --  -------------------------------------------------
         ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );

NOT of a 'U' is a 'U'.

With a waveform viewer that shows 'U' values:

waveform viewer showing 'U'

This was done with ghdl and gtkwave, and an added testbench. The only change to architecture arc of Taraefa09 was to add sq0_n and assign it in a concurrent signal:

INV:  sq0_n <= not sq0;

Along with substituting sq0_n for sq0 in the first actual of I1: Mux2x1. ghdl doesn't support a function used with the actual of inputs.

And the solution is to a) reset the flip flops or b) use type BIT or c) provide default values for q0 in FFT. Choice a) would be preferred unless there's something about your target device that provides known default (initial) values.

It turns out there's something else wrong as well:

ENTITY FFT IS
    PORT(
        clk: IN STD_LOGIC;
        q: OUT STD_LOGIC
    );
END FFT;

ARCHITECTURE Arc OF FFT IS
    SIGNAL sq: STD_LOGIC := '0' ;  -- choice c) 
    BEGIN
        PROCESS(clk)
        BEGIN
            IF(clk'event AND clk='1') THEN -- clk'event: é o evento de subida/descida. 
                sq <= (not sq);         -- changed target from q to sq
            END IF;
        END PROCESS;

    BUF: q <= sq;   -- added concurrent statement

    END Arc;

This represents choice c) a default value for the actual q in the flip flop (named sq). The type of flip flop is known as a toggle flip flop or T flip flop.

At this point we get:

fixed simulation

VHDL - Asynchronous up/down counter

1 Answers