If we have the following configuration for example, how can we calculate the size of the page table
A computer uses 46–bit virtual address, 32–bit physical address, and a three–level page table organization. The page table base register stores the base address of the first–level table, which occupies exactly one page. Each entry of the first level page table stores the base address of a page of the second–level table. Each entry of the second level page table stores the base address of a page of the third–level table. Each entry of the third level page table stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16 way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.