cache simulation and page faults

0
votes

I hope this isn't a duplicate.

Question regarding cache and virtual memory simulation:

  • suppose a blocking cache (a blocking cache is a cache that waits until the transfer from memory to cache is complete before delivering data to CPU)

What happens if:

  • CPU asks for an instruction not present in instruction cache (there's a miss)
  • instruction cache asks for data to MMU/memory
  • the MMU reports a page fault
  • The CPU receives an interrupt from MMU that alerts about the page fault
  • CPU jumps to hardwired address that contains code for handling page fault
  • instruction fetch stage asks for the first instruction (from page fault handling) to cache

Now my question: how cache will delivery page fault handling code to CPU if it is waiting for main memory to delivery the other data (the one that caused page fault)?

I came up with this solution: improve my cache so that both CPU and cache receives the page fault signal; cache stores its state, receives and deliveries page fault handling code to CPU and then restore its previous states.

This is what I came up with, but is this the correct/valid and efficient way to do?

1
cachingsimulationvirtual-memory

1 Answers

0
votes

The CPU and cache don't wait for the missing data.

Generally the page fault generates some type of interrupt to the CPU, suspending the original instruction stream. When the page fault handler returns, the original instruction stream resumes, starting with the instruction that wasn't present in the cache the first time.